Coverage-driven Functional Test Generation for Processor Validation using Formal Methods

Functional validation is one of the major bottlenecks in processor design: up to 70% of the design development time and resources are spent on functional verification. Simulation is the most widely used form of microprocessor validation. A major challenge in simulation-based validation is how to reduce the overall validation time and resources. Traditionally, billions of random tests are used during simulation and the lack of a comprehensive functional coverage metric makes it difficult to measure the verification progress. Directed test generation is a promising approach in terms of the volume of test set but poses several challenges. One of the major challenges is how to generate directed tests for complex processor designs for efficient functional validation. This paper presents functional coverage-driven test generation techniques using formal methods. We present fault models based on the functionality of pipelined processors. These fault models are used to define the functional coverage metric to measure the verification progress. We have developed automatic test generation techniques using model checking and SAT solving methods. The experiments using MIPS processor demonstrate the feasibility and usefulness of the proposed functional validation methodology.